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publication number 25261 revision b amendment +10 issue date december 21, 2005 am29lv641mh/l data sheet retired product this product has been retired and is not avai lable for designs. for new and current designs, s29gl064a supersedes am29lv641m h/l and is th e factory-recommended migration path. please refer to the s29gl064a datasheet for specifications and ordering information. availability of this document is retained for refere nce and historical purposes only. april 2005 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these produc ts will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of n ormal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions.
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this data sheet states amd?s current technical specif ications regarding the products described herein. this data sheet may be revised by subsequent versions or modi fications due to changes in technical specifications. refer to amd?s website (www.amd.com) for the latest information. publication# 25261 rev: b amendment/ +10 issue date: december 21, 2005 am29lv641mh/l 64 megabit (4 m x 16-bit) mirrorbit ? 3.0 volt-only uniform sector flash memory with versatilei/o ? control distinctive characteristics architectural advantages ? single power supply operation ? 3 v for read, erase, and program operations ? versatilei/o ? control ? device generates data output voltages and tolerates data input voltages on ce# and the dq inputs/outputs as determined by the voltage on the v io pin; operates from 1.65 to 3.6 v ? manufactured on 0.23 m mirrorbit process technology ? secsi ? (secured silicon) sector region ? 128-word sector for permanent, secure identification through an 8-word random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer ? flexible sector architecture ? one hundred twenty-eight 32 kword sectors ? compatibility with jedec standards ? provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection ? minimum 100,000 erase cycle guarantee per sector ? 20-year data retention at 125 c performance characteristics ? high performance ? 90 ns access time ? 25 ns page read times ? 0.5 s typical sector erase time ? 22 s typical effective write buffer word programming time: 16-word write buffer reduces overall programming time for multiple-word updates ? 4-word page read buffer ? 16-word write buffer ? low power consumption (typ ical values at 3.0 v, 5 mhz) ? 30 ma typical active read current ? 50 ma typical erase/program current ? 1 a typical standby mode current ? package options ? 48-pin tsop software & hardware features ? software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resu me: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? unlock bypass program command reduces overall multiple-word programming time ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices ? hardware features ? sector group protection: hardware-level method of preventing write operations within a sector group ? temporary sector unprotect: v id -level method of changing code in locked sectors ? acc (high voltage) input accelerates programming time for higher throughput during system production ? write protect input (wp#) prot ects first or last sector regardless of sector protection settings ? hardware reset input (reset#) resets device this product has been retired and is not available for designs. for new and current designs, s29gl064a supersedes am29lv641m h/ l and is the factory-recommended migration path. please refer to the s29gl064a datasheet for specifications and ordering information. availability of this document is retained for reference and historical purposes only.
2 am29lv641mh/l december 21, 2005 datasheet general description the am29lv641mh/l is a 64 mbit, 3.0 volt single power supply flash memory devices organized as 4,194,304 words. the devices have a 16-bit wide data bus, and can be programmed either in the host system or in standard eprom programmers. an access time of 90, 100, 110, or 120 ns is available. note that each access time has a specific operating voltage range (v cc ) and an i/o voltage range (v io ), as specified in the product selector guide and the order- ing information sections. the device is offered in a 48-pin tsop package. each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0 volt power supply for both read and write functions. in addition to a v cc input, a high-voltage accelerated program (acc) input provides shorter programming times through increased current. this feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. the device is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the device using standard microprocessor write timing. write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase oper- ation has begun, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits to de- termine whether the operation is complete. to facilitate programming, an unlock bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. the versatilei/o? (v io ) control allows the host sys- tem to set the voltage levels that the device generates and tolerates on the ce# control input and dq i/os to the same voltage level that is asserted on the v io pin. refer to the ordering information section for valid v io options. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program sus- pend/program resume feature enables the host sys- tem to pause a program operation in a given sector to read any other sector and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the secsi ? (secured silicon) sector provides a 128-word area for code or data that can be perma- nently protected. once this sector is protected, no fur- ther changes within the sector can occur. the write protect (wp#) feature protects the first or last sector by asserting a logic low on the wp# pin. the protected sector will still be protected even during accelerated programming. amd mirrorbit flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection.
december 21, 2005 am29lv641mh/l 3 datasheet mirrorbit 64 mbit device family related documents to download related documents, click on the following links or go to www.amd.com flash memory prod- uct information mirrorbit flash information te c h - nical documentation. mirrorbit? flash memory write buffer programming and page buffer read implementing a common layout for amd mirrorbit and intel strataflash memory devices amd mirrorbit? white paper migrating from single-byte to three-byte device ids device bus sector architecture packages v io ry/by# wp#, acc wp# protection lv065mu x8 uniform (64k-byte) 48-pin tsop (std. & rev. pinout), 63-ball fbga yes yes acc only no wp# lv640mt/b x8/x16 boot (8x8k-byte @ top & bottom) 48-pin tsop, 63-ball fine-pitch bga, 64-ball fortified bga no yes wp#/acc pin 2 x 8 kbyte top or bottom lv640mh/l x8/x16 uniform (64k-byte) 56-pin tsop (std. & rev. pinout), 64 fortified bga yes yes wp#/acc pin 1 x 64 kbyte high or low lv641mh/l x16 uniform (32k-word) 48-pin tsop (std. & rev. pinout) yes no separate wp# and acc pins 1 x 32 kword top or bottom lv640mu x16 uniform (32k-word) 63-ball fine-pitch bga, 64 ball fortified bga yes yes acc only no wp#
4 am29lv641mh/l december 21, 2005 datasheet table of contents continuity of specificat ions ....................................................... i for more information ................................................................. i product selector guide . . . . . . . . . . . . . . . . . . . . . 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 6 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ordering information . . . . . . . . . . . . . . . . . . . . . . . 8 device bus operations . . . . . . . . . . . . . . . . . . . . . 9 table 1. device bus operations .......................................................9 versatileio ? (v io ) control ....................................................... 9 requirements for reading array data ..................................... 9 page mode read .................................................................... 10 writing commands/command sequences ............................ 10 write buffer ............................................................................. 10 accelerated program operation ............................................. 10 autoselect functions .............................................................. 10 standby mode ........................................................................ 10 automatic sleep mode ........................................................... 10 reset#: hardware reset pin ............................................... 11 output disable mode .............................................................. 11 table 2. sector address table ........................................................12 autoselect mode..................................................................... 14 table 3. autoselect codes, (high voltage method) .......................14 sector group protection and unprotection ............................. 15 table 4. sector group protection /unprotection address table .....15 write protect (wp#) ................................................................ 16 temporary sector group unprotect ....................................... 16 figure 1. temporary sector group unprotect operation................ 16 figure 2. in-system sector group protect/unprotect algorithms ... 17 secsi (secured silicon) sect or flash memory region .......... 18 table 5. secsi sector contents ......................................................18 figure 3. secsi sector protect verify.............................................. 19 hardware data protection ...................................................... 19 low vcc write inhibit ............................................................ 19 write pulse ?glitch? protection ............................................... 19 logical inhibit .......................................................................... 19 power-up write inhibit ............................................................ 19 common flash memory interfac e (cfi) . . . . . . . 19 table 6. cfi query identifi cation string .............................. 20 table 7. system interface string......................................................20 table 8. device geometry definition................................... 21 table 9. primary vendor-specific extended query............. 22 command definitions . . . . . . . . . . . . . . . . . . . . . 22 reading array data ................................................................ 22 reset command ..................................................................... 23 autoselect command sequence ............................................ 23 enter secsi sector/exit secsi sector command sequence .. 23 word program command sequence ..................................... 23 unlock bypass command sequence ..................................... 24 write buffer programming ...................................................... 24 accelerated program .............................................................. 25 figure 4. write buffer programming operation............................... 26 figure 5. program operation .......................................................... 27 program suspend/program resume command sequence ... 27 figure 6. program suspend/program resume............................... 28 chip erase command sequence ........................................... 28 sector erase command s equence ........................................ 28 erase suspend/erase resu me commands ........................... 29 figure 7. erase operation.............................................................. 30 command definiti ons ............................................................. 31 table 10. command definitions...................................................... 31 write operation status . . . . . . . . . . . . . . . . . . . . . 32 dq7: data# polling ................................................................. 32 figure 8. data# polling algorithm .................................................. 32 dq6: toggle bit i .................................................................... 33 figure 9. toggle bit algorithm........................................................ 33 dq2: toggle bit ii ................................................................... 34 reading toggle bi ts dq6/dq2 ............................................... 34 dq5: exceeded timing limits ................................................ 34 dq3: sector erase timer ....................................................... 34 dq1: write-to-buffer abort ..................................................... 35 table 11. write operation status ................................................... 35 absolute maximum ratings. . . . . . . . . . . . . . . . . 36 figure 10. maximum negative overshoot waveform ................... 36 figure 11. maximum positive overshoot waveform..................... 36 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 36 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37 test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 12. test setup.................................................................... 38 table 12. test specifications ......................................................... 38 key to switching waveforms. . . . . . . . . . . . . . . . 38 figure 13. input waveforms and measurement levels...................................................................... 38 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39 read-only operations ........................................................... 39 figure 14. read operation timings ............................................... 39 figure 15. page read timings ...................................................... 40 hardware reset (reset#) .................................................... 41 figure 16. read operation timings ............................................... 41 figure 17. reset timings ............................................................... 42 erase and program operations .............................................. 43 figure 18. program operation timings.......................................... 44 figure 19. accelerated program timing diagram.......................... 44 figure 20. chip/sector erase operation timings .......................... 45 figure 21. data# polling timings (during embedded algorithms)...................................................... 46 figure 22. toggle bit timings (during embedded algorithms)...................................................... 47 figure 23. dq2 vs. dq6................................................................. 47 temporary sector unprotect .................................................. 48 figure 24. temporary sector grou p unprotect timing diagram ... 48 figure 25. sector group protect and unprotect timing diagram .. 49 alternate ce# controlled erase and program operations ..... 50 figure 26. alternate ce# cont rolled write (erase/program) operation timings.......................................................................... 51 erase and programming performance. . . . . . . . 52 latchup characteristics . . . . . . . . . . . . . . . . . . . . 52 tsop pin capacitance . . . . . . . . . . . . . . . . . . . . . 53 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 54 ts 048?48-pin standard thin small outline package ......... 54 tsr048?48-pin reverse thin small outline package ......... 55 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 56
december 21, 2005 am29lv641mh/l 5 datasheet product selector guide notes: 1. see ?ac characteristics? for full specifications. 2. for the am29lv641mh/l device, the last numeric digit in the speed option (e.g. 101 , 112 , 120 ) is used for internal purposes only. please use opns as listed when placing orders. block diagram part number am29lv641mh/l speed option v cc = 3.0?3.6 v 90r (v io = 3.0?3.6 v) 101r (v io = 2.7?3.6 v) 112r (v io = 1.65?3.6 v) 120r (v io = 1.65?3.6 v) v cc = 2.7?3.6 v 101 (v io = 2.7?3.6 v) 112 (v io = 1.65?3.6 v) 120 (v io = 1.65?3.6 v) max. access time (ns) 90 100 110 120 max. ce# access time (ns) 90 100 110 120 max. page access time (t pac c ) 25 30 30 40 30 40 max. oe# access time (ns) 25 30 30 40 30 40 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v io we# wp# acc ce# oe# stb stb dq0 ? dq15 sector switches reset# data latch y-gating cell matrix address latch a21?a0
6 am29lv641mh/l december 21, 2005 datasheet connection diagrams 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 a21 a20 we# reset# acc wp# a19 a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 v io v ss dq15 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48-pin standard tsop 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 a21 a20 we# reset# acc wp# a19 a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 v io v ss dq15 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48-pin reverse tsop
december 21, 2005 am29lv641mh/l 7 datasheet pin description a21?a0 = 22 address inputs dq15?dq0 = 16 data inputs/outputs ce# = chip enable input oe# = output enable input we# = write enable input wp# = hardware write protect input acc = acceleration input reset# = hardware reset pin input v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v io = output buffer power v ss = device ground nc = pin not connected internally logic symbol 22 16 dq15?dq0 a21?a0 ce# oe# we# reset# acc wp# v io
8 am29lv641mh/l december 21, 2005 datasheet ordering information standard products amd standard products are available in several packages and o perating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. note: for the am29lv641mh/l device, the last numeric digit in the speed option (e.g. 101 , 112 , 120 ) is used for internal purposes only. please use opns as listed when placing orders. am29lv641m h 120r e i temperature range i = industrial (?40 c to +85 c) package type e = 48-pin thin small outline package (tsop) standard pinout (ts 048) f = 48-pin thin small outline package (tsop) reverse pinout (tsr048) speed option see product selector guide and valid combinations sector architecture and sector write protection (wp# = 0) h = uniform sector device, highest address sector protected l = uniform sector device, lowest address sector protected device number/description am29lv641mh/l 64 megabit (4 m x 16-bit) mirrorbit uniform sector flash memory with versatileio ? control 3.0 volt-only read, program, and erase valid combinations for tsop packages speed (ns) v io range v cc range am29lv641mh90r, am29lv641ml90r ei, fi 90 3.0? 3.6 v 3.0? 3.6 v am29lv641mh101, am29lv641ml101 100 2.7?3.6 v 2.7? 3.6 v am29lv641mh112, am29lv641ml112 110 1.65?3.6 v am29lv641mh120, am29lv641ml120 120 1.65?3.6 v am29lv641mh101r, am29lv641ml101r 100 2.7?3.6 v 3.0? 3.6 v am29lv641mh112r, am29lv641ml112r 110 1.65?3.6 v am29lv641mh120r, am29lv641ml120r 120 1.65?3.6 v
december 21, 2005 am29lv641mh/l 9 datasheet device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are a21:a0. sector addresses are a21:a15. 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector group protection and unprotection? section. 3. if wp# = v il , the first or last sector re mains protected. if wp# = v ih , the first or last sector will be protected or unprotected as determined by the method described in ?sec tor group protection and unprotection?. all sectors are unprotected when shipped from the factory (the secsi sector may be factory protected depending on version ordered.) 4. d in or d out as required by command sequence, data polling, or sector protect algorithm (see figure 2). versatileio ? (v io ) control the versatileio? (v io ) control allows the host system to set the voltage levels that the device generates and tolerates on ce# and dq i/os to the same voltage level that is asserted on v io . see ?ordering informa- tion? on page 8 for v io options on this device. for example, a v i/o of 1.65?3.6 volts allows for i/o at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 v devices on the same data bus. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid operation ce# oe# we# reset# wp# acc addresses (note 2) dq0? dq15 read l l h h xl/h a in d out write (program/erase) l h l h (note 3) l/h a in (note 4) accelerated program l h l h (note 3) v hh a in (note 4) standby v cc 0.3 v xx v cc 0.3 v xh xhigh-z output disable l h h h xl/h xhigh-z reset x x x l xl/h xhigh-z sector group protect (note 2) l h l v id hl/h sa, a6 =l, a3=l, a2=l, a1=h, a0=l (note 4) sector group unprotect (note 2) lhl v id hl/h sa, a6=h, a3=l, a2=l, a1=h, a0=l (note 4) temporary sector group unprotect xxx v id hl/h a in (note 4)
10 am29lv641mh/l december 21, 2005 datasheet data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac read-only operations table for timing speci- fications and to figure 14 for the timing diagram. refer to the dc characteristics ta ble for the active current specification on reading array data. page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read oper- ation. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 words. the appropriate page is se- lected by the higher address bits a(max)?a2. address bits a1?a0 determine the specific word within a page. this is an asynchronous operation; the microproces- sor supplies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pac c . when ce# is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode ac- cesses are obtained by keeping the ?read-page ad- dresses? constant and changing the ?intra-read page? addresses. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word, instead of four. the ?word program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 2 indicates the address space that each sector occupies. refer to the dc characteristics table for the active current specification for the write mode. the ac char- acteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the system to write a maximum of 16 words in one programming operation. this results in faster effective programming time than the standard programming algorithms. see ?write buffer? for more information. accelerated program operation the device offers accelerated program operations through the acc function. this function is primarily in- tended to allow faster manufacturing throughput dur- ing system production. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the acc pin returns the device to normal op- eration. note that the acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autose- lect command sequence sections for more informa- tion. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device re- quires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. refer to the dc characteristics table for the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard ad- dress access timings provide new data when ad-
december 21, 2005 am29lv641mh/l 11 datasheet dresses are changed. while in sleep mode, output data is latched and always available to the system. refer to the dc characteristics table for the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for th e duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. refer to the ac characteristics tables for reset# pa- rameters and to figure 17 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
12 am29lv641mh/l december 21, 2005 datasheet table 2. sector address table sector a21?a15 16-bit address range (in hexadecimal) sector a21?a15 16-bit address range (in hexadecimal) sa0 0000000 000000?007fff sa32 0100000 100000?107fff sa1 0000001 00 8000?00ffff sa33 0100001 108000?10ffff sa2 0000010 010000?017fff sa34 0100010 110000?117fff sa3 0000011 01 8000?01ffff sa35 0100011 118000?11ffff sa4 0000100 020000?027fff sa36 0100100 120000?127fff sa5 0000101 02 8000?02ffff sa37 0100101 128000?12ffff sa6 0000110 030000?037fff sa38 0100110 130000?137fff sa7 0000111 03 8000?03ffff sa39 0100111 138000?13ffff sa8 0001000 040000?047fff sa40 0101000 140000?147fff sa9 0001001 04 8000?04ffff sa41 0101001 148000?14ffff sa10 0001010 050000?057fff sa42 0101010 150000?157fff sa11 0001011 05 8000?05ffff sa43 0101011 158000?15ffff sa12 0001100 060000?067fff sa44 0101100 160000?167fff sa13 0001101 06 8000?06ffff sa45 0101101 168000?16ffff sa14 0001110 070000?077fff sa46 0101110 170000?177fff sa15 0001111 07 8000?07ffff sa47 0101111 178000?17ffff sa16 0010000 080000?087fff sa48 0110000 180000?187fff sa17 0010001 08 8000?08ffff sa49 0110001 188000?18ffff sa18 0010010 090000?097fff sa50 0110010 190000?197fff sa19 0010011 09 8000?09ffff sa51 0110011 198000?19ffff sa20 0010100 0a 0000?0a7fff sa52 0110100 1a000 0?1a7fff sa21 0010101 0a 8000?0affff sa53 0110101 1a80 00?1affff sa22 0010110 0b 0000?0b7fff sa54 0110110 1b000 0?1b7fff sa23 0010111 0b 8000?0bffff sa55 0110111 1b80 00?1bffff sa24 0011000 0c 0000?0c7fff sa56 0111000 1c000 0?1c7fff sa25 0011001 0c 8000?0cffff sa57 0111001 1c80 00?1cffff sa26 0011010 0d 0000?0d7fff sa58 0111010 1d000 0?1d7fff sa27 0011011 0d 8000?0dffff sa59 0111011 1d80 00?1dffff sa28 0011100 0e 0000?0e7fff sa60 0111100 1e000 0?1e7fff sa29 0011101 0e 8000?0effff sa61 0111101 1e80 00?1effff sa30 0011110 0f 0000?0f7fff sa62 0111110 1f000 0?1f7fff sa31 0011111 0f 8000?0fffff sa63 0111111 1f80 00?1fffff sa64 1000000 200000?207fff sa96 1100000 300000?307fff sa65 1000001 20 8000?20ffff sa97 1100001 308000?30ffff sa66 1000010 210000?217fff sa98 1100010 310000?317fff sa67 1000011 21 8000?21ffff sa99 1100011 318000?31ffff sa68 1000100 220000?227fff sa100 1100100 320000?327fff sa69 1000101 22 8000?22ffff sa101 1100101 328000?32ffff sa70 1000110 230000?237fff sa102 1100110 330000?337fff sa71 1000111 23 8000?23ffff sa103 1100111 338000?33ffff sa72 1001000 240000?247fff sa104 1101000 340000?347fff sa73 1001001 24 8000?24ffff sa105 1101001 348000?34ffff sa74 1001010 250000?257fff sa106 1101010 350000?357fff sa75 1001011 25 8000?25ffff sa107 1101011 358000?35ffff
december 21, 2005 am29lv641mh/l 13 datasheet note: all sectors are 32 kwords in size. sa76 1001100 260000?267fff sa108 1101100 360000?367fff sa77 1001101 26 8000?26ffff sa109 1101101 368000?36ffff sa78 1001110 270000?277fff sa110 1101110 370000?377fff sa79 1001111 27 8000?27ffff sa111 1101111 378000?37ffff sa80 1010000 280000?287fff sa112 1110000 380000?387fff sa81 1010001 28 8000?28ffff sa113 1110001 388000?38ffff sa82 1010010 290000?297fff sa114 1110010 390000?397fff sa83 1010011 29 8000?29ffff sa115 1110011 398000?39ffff sa84 1010100 2a 0000?2a7fff sa116 1110100 3a000 0?3a7fff sa85 1010101 2a 8000?2affff sa117 1110101 3a80 00?3affff sa86 1010110 2b 0000?2b7fff sa118 1110110 3b000 0?3b7fff sa87 1010111 2b 8000?2bffff sa119 1110111 3b80 00?3bffff sa88 1011000 2c 0000?2c7fff sa120 1111000 3c000 0?3c7fff sa89 1011001 2c 8000?2cffff sa121 1111001 3c80 00?3cffff sa90 1011010 2d 0000?2d7fff sa122 1111010 3d000 0?3d7fff sa91 1011011 2d 8000?2dffff sa123 1111011 3d80 00?3dffff sa92 1011100 2e 0000?2e7fff sa124 1111100 3e000 0?3e7fff sa93 1011101 2e 8000?2effff sa125 1111101 3e80 00?3effff sa94 1011110 2f 0000?2f7fff sa126 1111110 3f000 0?3f7fff sa95 1011111 2f 8000?2fffff sa127 1111111 3f80 00?3fffff table 2. sector address table (continued) sector a21?a15 16-bit address range (in hexadecimal) sector a21?a15 16-bit address range (in hexadecimal)
14 am29lv641mh/l december 21, 2005 datasheet autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on address pin a9. address pins a6, a3, a2, a1, and a0 must be as shown in table 3. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see table 2). table 3 shows the remain- ing address bits that are don?t care. when all neces- sary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 10. this method does not require v id . refer to the autoselect com- mand sequence section for more information. table 3. autoselect codes, (high voltage method) legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. description ce# oe# we# a21 to a15 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq15 to dq0 manufacturer id : amd l l h x x v id x l x l l l 0001h device id cycle 1 ll h x x v id xlx llh 227eh cycle 2 h h l 2213h cycle 3 h h h 2201h sector protection verification ll hsax v id xlxlhl xx01h (protected), xx00h (unprotected) secsi sector indicator bit (dq7), wp# protects highest address sector ll h x x v id xlxlhh xx98h (factory locked), xx18h (not factory locked) secsi sector indicator bit (dq7), wp# protects lowest address sector ll h x x v id xlxlhh xx88h (factory locked), xx08h (not factory locked)
december 21, 2005 am29lv641mh/l 15 datasheet sector group protection and unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. in this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see table 4). the hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. sector group protection/unprotection can be implemented via two methods. sector protection/unprotection requires v id on the re- set# pin only, and can be implemented either in-sys- tem or via programming equipment. figure 2 shows the algorithms and figure 25 shows the timing dia- gram. this method uses standard microprocessor bus cycle timing. for sector group unprotect, all unpro- tected sector groups must first be protected prior to the first sector group unprotect write cycle. the device is shipped with all sector groups unpro- tected. amd offers the option of programming and pro- tecting sector groups at its factory prior to shipping the device through amd?s expressflash? service. con- tact an amd representative for details. it is possible to determine whether a sector group is protected or unprotected. see the autoselect mode section for details. table 4. sector group protection/unprotection address table note: all sector groups are 128 kwords in size. sector group a21?a17 sa0?sa3 00000 sa4?sa7 00001 sa8?sa11 00010 sa12?sa15 00011 sa16?sa19 00100 sa20?sa23 00101 sa24?sa27 00110 sa28?sa31 00111 sa32?sa35 01000 sa36?sa39 01001 sa40?sa43 01010 sa44?sa47 01011 sa48?sa51 01100 sa52?sa55 01101 sa56?sa59 01110 sa60?sa63 01111 sa64?sa67 10000 sa68?sa71 10001 sa72?sa75 10010 sa76?sa79 10011 sa80?sa83 10100 sa84?sa87 10101 sa88?sa91 10110 sa92?sa95 10111 sa96?sa99 11000 sa100?sa103 11001 sa104?sa107 11010 sa108?sa111 11011 sa112?sa115 11100 sa116?sa119 11101 sa120?sa123 11110 sa124?sa127 11111
16 am29lv641mh/l december 21, 2005 datasheet write protect (wp#) the write protect function provides a hardware method of protecting the first or last sector without using v id . if the system asserts v il on the wp# pin, the device disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected using the method described in ?sector group protection and unprotection?. note that if wp# is at v il when the device is in the standby mode, the maximum input load current is increased. see the table in ?dc characteristics?. if the system asserts v ih on the wp# pin, the device reverts to whether the first or last sector was previ- ously set to be protected or unprotected using the method described in ?sector group protection and unprotection?. temporary sector group unprotect ( note: in this device, a sector gr oup consists of four adjacent sectors that are prot ected or unprotected at the same time (see table 4). this feature allows temporary unprotection of previ- ously protected sector groups to change data in-sys- tem. the sector group unprotect mode is activated by setting the reset# pin to v id . during this mode, for- merly protected sector groups can be programmed or erased by selecting the sector group addresses. once v id is removed from the reset# pin, all the previously protected sector groups are protected again. figure 1 shows the algorithm, and figure 24 shows the timing diagrams, for this feature. figure 1. temporary sector group unprotect operation start perform erase or program operations reset# = v ih temporary sector group unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sector gr oups unprotected (if wp# = v il , the first or last sector will remain protected). 2. all previously protected sector groups are protected once again.
december 21, 2005 am29lv641mh/l 17 datasheet figure 2. in-system sector group protect/unprotect algorithms sector group protect: write 60h to sector group address with a6?a0 = 0xx0010 set up sector group address wait 150 s verify sector group protect: write 40h to sector group address with a6?a0 = 0xx0010 read from sector group address with a6?a0 = 0xx0010 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector group protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector group unprotect mode no sector group unprotect: write 60h to sector group address with a6?a0 = 1xx0010 set up first sector group address wait 15 ms verify sector group unprotect: write 40h to sector group address with a6?a0 = 1xx0010 read from sector group address with a6?a0 = 1xx0010 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector group verified? remove v id from reset# write reset command sector group unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector group unprotect mode no all sector groups protected? yes protect all sector groups: the indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address set up next sector group address no yes no yes no no yes no sector group protect algorithm sector group unprotect algorithm first write cycle = 60h? protect another sector group? reset plscnt = 1
18 am29lv641mh/l december 21, 2005 datasheet secsi (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 128 words in length, and uses a secsi sector indicator bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the secu- rity of the esn once the product is shipped to the field. amd offers the device with the secsi sector either factory locked or customer lockable. the fac- tory-locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sector indicator bit permanently set to a ?1.? the cus- tomer-lockable version is shipped with the secsi sec- tor unprotected, allowing customers to program the sector after receiving the device. the customer-lock- able version also has the secsi sector indicator bit permanently set to a ?0.? thus, the secsi sector indi- cator bit prevents customer-lockable devices from being used to replace devices that are factory locked. the secsi sector address space in this device is allo- cated as follows: the system accesses the secsi sector through a command sequence (see ?enter secsi sector/exit secsi sector command sequence?). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the ad- dresses normally occupied by the first sector (sa0). this mode of operation continues until the system is- sues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. factory locked: secsi sector programmed and protected at the factory in devices with an esn, the secsi sector is protected when the device is shipped from the factory. the secsi sector cannot be modified in any way. a factory locked device has an 8-word random esn at addresses 000000h?000007h. customers may opt to have their code programmed by amd through the amd expressflash service. the de- vices are then shipped from amd?s factory with the secsi sector permanently locked. contact an amd representative for details on using amd?s express- flash service. customer lockable: secsi sector not programmed or protected at the factory as an alternative to the factory-locked version, the de- vice may be ordered such that the customer may pro- gram and protect the 128-word secsi sector. the system may program the secsi sector using the write-buffer, accelerated and/or unlock bypass meth- ods, in addition to the standard programming com- mand sequence. see command definitions . programming and protecting the secsi sector must be used with caution since, once protected, there is no procedure available for unprotecting the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. the secsi sector area can be protected using one of the following procedures: write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ex- cept that reset# may be at either v ih or v id . this allows in-system protection of the secsi sector without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. to verify the protect/unprotect status of the secsi sector, follow the algorithm shown in figure 3. once the secsi sector is programmed, locked and verified, the system must write the exit secsi sector region command sequence to return to reading and writing within the remainder of the array. table 5. secsi sector contents secsi sector address range standard factory locked expressflash factory locked customer lockable 000000h?000007h esn esn or determined by customer determined by customer 000008h?00007fh unavailable determined by customer
december 21, 2005 am29lv641mh/l 19 datasheet figure 3. secsi sector protect verify hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 10 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 6?9. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 6?9. the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd .com/flash/cfi. alterna- tively, contact an amd representative for copies of these documents. write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
20 am29lv641mh/l december 21, 2005 datasheet table 6. cfi query identification string table 7. system interface string addresses (x16) data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) addresses (x16) data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0007h typical timeout per single byte/word write 2 n s 20h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0001h max. timeout for byte/word write 2 n times typical 24h 0005h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
december 21, 2005 am29lv641mh/l 21 datasheet table 8. device geometry definition addresses (x16) data description 27h 0017h device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0001h number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 007fh 0000h 0000h 0001h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 0000h 0000h 0000h 0000h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
22 am29lv641mh/l december 21, 2005 datasheet table 9. primary vendor-specific extended query command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. table 10 defines the valid register command sequences. writing incorrect address and data val- ues or writing them in the improper sequence may place the device in an unknown state. a reset com- mand is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any addresses (x16) data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0008h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0010b = 0.23 m mirrorbit 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0004h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0004h sector protect/unprotect scheme 04 = 29lv800 mode 4ah 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0001h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0004h/ 0005h top/bottom boot sector flag 00h = uniform device without wp# protect, 02h = bottom boot device, 03h = top boot device, 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h 0001h program suspend 00h = not supported, 01h = supported
december 21, 2005 am29lv641mh/l 23 datasheet non-erase-suspended sector. after completing a pro- gramming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase op- eration, or if the device is in the autoselect mode. see the next section, reset command , for more informa- tion. see also requirements for reading array data in the device bus operations section for more information. the read-only operations table provides the read pa- rameters, and figure 14 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the de- vice entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a write buffer pro- gramming operation, the system must write the write-to-buffer-abort reset command sequence to reset the device for the next operation. autoselect command sequence the autoselect command sequence allows the host system to read several identifier codes at specific ad- dresses: note: the device id is read over three cycles. sa = sector address table 10 shows the address and data requirements. this method is an alternative to that shown in table 3, which is intended for prom programmers and re- quires v id on address pin a9. the autoselect com- mand sequence may be written to an address that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the de- vice is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence the system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in erase suspend). enter secsi sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing an 8-word random electronic serial num- ber (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector command sequence returns the de- vice to normal operation. table 10 shows the address and data requirements for both command sequences. see also ?secsi (secured silicon) sector flash memory region? for further information. note that the acc function and unlock bypass modes are not avail- able when the secsi sector is enabled. word program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further identifier code a7:a0 manufacturer id 00h device id, cycle 1 01h device id, cycle 2 0eh device id, cycle 3 0fh secsi sector factory protect 03h sector protect verify (sa)02h
24 am29lv641mh/l december 21, 2005 datasheet controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 10 shows the address and data requirements for the word program command sequence. when the embedded program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7 or dq6. refer to the write operation status sec- tion for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. note that the acc function and unlock bypass modes are not available when the secsi sector is enabled. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. the unlock bypass command sequence is initiated by first writing two un- lock cycles. this is followed by a third write cycle con- taining the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle un- lock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program com- mand, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. table 10 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h. the second cycle must contain the data 00h. the device then returns to the read mode. write buffer programming write buffer programming allows the system write to a maximum of 16 words in one programming operation. this results in faster effective programming time than the standard programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load com- mand written at the sector address in which program- ming will occur. the fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. for example, if the system will pro- gram 6 unique address locations, then 05h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the program buffer to flash command. the number of locations to program cannot exceed the size of the write buffer or the operation will abort. the fifth cycle writes the first address location and data to be programmed. the write-buffer-page is se- lected by address bits a max ?a 4 . all subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. the system then writes the remaining address/data pairs into the write buffer. write buffer locations may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be per- formed across multiple write-buffer pages. this also means that write buffer programming cannot be per- formed across multiple sectors. if the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. note that if a write buffer address location is loaded multiple times, the addre ss/data pair counter will be decremented for every data load operation. the host system must therefore account for loading a write-buffer location more than once. the counter dec- rements for each data load operation, not for each unique write-buffer-address location. note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. once the specified number of write buffer locations have been loaded, the system must then write the pro- gram buffer to flash command at the sector address. any other address and data combination aborts the write buffer programming operation. the device then begins programming. data polling should be used while monitoring the last address location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to determine the device status during write buffer programming.
december 21, 2005 am29lv641mh/l 25 datasheet the write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways: load a value that is greater than the page buffer size during the number of locations to program step. write to an address in a sector different than the one specified during the write-buffer-load com- mand. write an address/data pair to a different write-buffer-page than the one selected by the starting address during the write buffer data load- ing stage of the operation. write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded), dq6 = toggle, and dq5=0. a write-to-buffer-abort reset command sequence must be written to reset the de- vice for the next operation. note that the full 3-cycle write-to-buffer-abort reset command sequence is re- quired when using write-buffer-programming features in unlock bypass mode. accelerated program the device offers accelerated program operations through the acc pin. when the system asserts v hh on the acc pin, the device automatically enters the un- lock bypass mode. the system may then write the two-cycle unlock bypass program command se- quence. the device uses the higher voltage on the acc pin to accelerate the operation. note that the acc pin must not be at v hh for operations other than accelerated programming, or device damage may re- sult. figure 5 illustrates the algorithm for the program oper- ation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 18 for timing diagrams.
26 am29lv641mh/l december 21, 2005 datasheet figure 4. write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1(wc) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pass read dq7 - dq0 at last loaded address read dq7 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1=1, write the write-buffer-programming-abort-reset command. if dq5=1, write the reset command. 4. see table 10 for command sequences required for write buffer programming. (note 3) (note 1) (note 2)
december 21, 2005 am29lv641mh/l 27 datasheet figure 5. program operation program suspend/ program resume command sequence the program suspend command allows the system to interrupt a programming operation or a write to buffer programming operation so that data can be read from any non-suspended sector. when the program sus- pend command is written during a programming pro- cess, the device halts the program operation within 5 s typical (maximum of 15 s) and updates the status bits. addresses are not required when writing the pro- gram suspend command. after the programming operation has been sus- pended, the system can read array data from any non-suspended sector. the program suspend com- mand may also be issued during a programming oper- ation while an erase is suspended. in this case, data may be read from any addresses not in erase sus- pend or program suspend. if a read is needed from the secsi sector area (one-time program area), then user must use the proper command sequences to enter and exit this region. note that the secsi sector, autoselect, and cfi functions are unavailable when an program operation is in progress. the system may also write the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. after the program resume command is written, the device reverts to programming. the system can deter- mine the status of the program operation using the dq7 or dq6 status bits, just as in the standard pro- gram operation. see write operation status for more information. the system must write the program resume com- mand (address bits are don?t care) to exit the program suspend mode and continue the programming opera- tion. further writes of the resume command are ig- nored. another program suspend command can be written after the device has resume programming. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 10 for program command sequence.
28 am29lv641mh/l december 21, 2005 datasheet figure 6. program suspend/program resume chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 10 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to the write operation status section for infor- mation on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that oc- curs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. note that the secsi sector, autoselect, and cfi functions are un- available when an erase operation is in progress. figure 7 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 20 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 10 shows the ad- dress and data requirements for the sector erase com- mand sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase ad- dress and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to en- sure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets the device to the read mode. the system must re- write the command sequence and any additional ad- dresses and commands. note that the secsi sector, autoselect, and cfi functions are unavailable when an erase operation is in progress. program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 s
december 21, 2005 am29lv641mh/l 29 datasheet the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7, dq6, or dq2 in the erasing sector. refer to the write opera- tion status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 7 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 20 section for timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sec- tor erase operation, including the 50 s time-out pe- riod during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a typi- cal of 5 s (maximum of 20 s) to suspend the erase operation. however, when the erase suspend com- mand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the device enters the erase-suspend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for infor- mation on these status bits. after an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. note: during an erase operation, this flash device per- forms multiple internal operations which are invisible to the system. when an erase operation is suspended, any of the internal operations that were not fully com- pleted must be restarted. as such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress will be impeded as a function of the number of suspends. the result will be a longer cumulative erase time than without suspends. note that the additional suspends do not affect device reliability or future performance. in most systems rapid erase/suspend activity occurs only briefly. in this ex- ample, erase performance will not be significantly im- pacted.
30 am29lv641mh/l december 21, 2005 datasheet figure 7. erase operation start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 10 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
december 21, 2005 am29lv641mh/l 31 datasheet command definitions table 10. command definitions legend: x = don?t care ra = read address of the memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 uniquely select any sector. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all other are write cycles. 4. during unlock and command cycles, when lower address bits are 555 or 2aa as shown in table, address bits higher than a11 and data bits higher than dq7 are don?t care. 5. no unlock or command cycles required when device is in read mode. 6. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when the device is in the autoselect mode, or if dq5 goes high while the device is providing status information. 7. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. see the autoselect command sequence section for more information. 8. the device id must be read in three cycles. 9. if wp# protects the highest address sector, the data is 98h for factory locked and 18h for not factory locked. if wp# protects the lowest address sector, the data is 88h for factory locked and 08h for not factor locked. 10. the data is 00h for an unprotected sector group and 01h for a protected sector group. 11. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 21, including "program buffer to flash" command. 12. command sequence resets device for next command after aborted write-to-buffer operation. 13. the unlock bypass command is required prior to the unlock bypass program command. 14. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 15. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 16. the erase resume command is valid only during the erase suspend mode. 17. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (notes) cycles bus cycles (notes 1?4) addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id (note 8) 6 555 aa 2aa 55 555 90 x01 227e x0e 2213 x0f 2201 secsi ? sector factory protect (note 9) 4 555 aa 2aa 55 555 90 x03 (note 9) sector group protect verify (note 10) 4 555 aa 2aa 55 555 90 (sa)x02 00/01 enter secsi sector region 3 555 aa 2aa 55 555 88 exit secsi sector region 4 555 aa 2aa 55 555 90 xxx 00 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer (note 11) 6 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 12) 3 555 aa 2aa 55 555 f0 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 13) 2 xxx a0 pa pd unlock bypass reset (note 14) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (note 15) 1 xxx b0 program/erase resume (note 16) 1 xxx 30 cfi query (note 17) 1 55 98
32 am29lv641mh/l december 21, 2005 datasheet write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 11 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is com- plete or in progress. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device out- puts on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is ac- tive for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on suc- cessive read cycles. table 11 shows the outputs for data# polling on dq7. figure 8 shows the data# polling algorithm. figure 21 in the ac characteristics section shows the data# polling timing diagram. figure 8. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
december 21, 2005 am29lv641mh/l 33 datasheet dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approxi- mately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the de- vice enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alterna- tively, the system can use dq7 (see the subsection on dq7: data# polling ). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 11 shows the outputs for toggle bit i on dq6. figure 9 shows the toggle bit algorithm. figure 22 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 23 shows the differences be- tween dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii . figure 9. toggle bit algorithm start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
34 am29lv641mh/l december 21, 2005 datasheet dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# to con- trol the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 11 to compare out- puts for dq2 and dq6. figure 9 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the dq6: toggle bit i subsection. figure 22 shows the toggle bit timing diagram. figure 23 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 9 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 9). dq5: exceeded timing limits dq5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not suc- cessfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? in all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between addi- tional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 11 shows the status of dq3 relative to the other status bits.
december 21, 2005 am29lv641mh/l 35 datasheet dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write-to-buffer-abort-reset command sequence to re- turn the device to reading array data. see write buffer programming section for more details. table 11. write operation status notes: 1. dq5 switches to ?1? when an embedded program, embedded er ase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status informat ion. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to moni tor the last loaded write-buffer address location. 4. dq1 switches to ?1? when the device has aborted the write-to-buffer operation. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle n/a program suspend mode program- suspend read program-suspended sector invalid (not allowed) non-program suspended sector data erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a non-erase suspended sector data erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 abort (note 4) dq7# toggle 0 n/a n/a 1
36 am29lv641mh/l december 21, 2005 datasheet absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . ?65 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . .?0.5 v to +4.0 v v io . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9 , oe#, acc, and reset# (note 2) . . . . . . . . . . . . . . . . . . . .?0.5 v to +12.5 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 10. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 11. 2. minimum dc input voltage on pins a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 10. maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for exten ded periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c supply voltages v cc (regulated voltage range) . . . . . . . . . . . 3.0?3.6 v v cc (full voltage range). . . . . . . . . . . . . . . . . 2.7?3.6 v v io (note 2) . . . . . . . . . . . . . . . . . . . . . . . . 1.65?3.6 v notes: 1. operating ranges define those limits between which the functionality of the device is guaranteed. 2. see ordering information section for valid v cc /v io range combinations. the i/os will not operate at 3 v when v io = 1.8 v. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 10. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 11. maximum positive overshoot waveform
december 21, 2005 am29lv641mh/l 37 datasheet dc characteristics cmos compatible notes: 1. on the wp#/acc pin only, the maxi mum input load current when wp# = v il is 5.0 a. 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v cc max. 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. tif v io < v cc , maximum v il for ce# and dq i/os is 0.3 v io . if v io < v cc , minimum v ih for ce# and dq i/os is 0.7 v io . maximum v ih for these connections is v io + 0.3 v 6. v cc voltage requirements. 7. v io voltage requirements. 8. not 100% tested. 9. includes ry/by# parameter symbol parameter description (notes) test conditions min typ max unit i li input load current (1) v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, acc input load current v cc = v cc max ; a9 = 12.5 v 35 a i lr reset leakage current v cc = v cc max ; reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (2, 3) ce# = v il, oe# = v ih , 5 mhz 15 20 ma 1 mhz 15 20 i cc2 v cc initial page read current (2, 3) ce# = v il, oe# = v ih 30 50 ma i cc3 v cc intra-page read current (2, 3) ce# = v il, oe# = v ih 10 20 ma i cc4 v cc active write current (3, 4) ce# = v il, oe# = v ih 50 60 ma i cc5 v cc standby current (3) ce#, reset# = v cc 0.3 v, wp# = v ih 15a i cc6 v cc reset current (3) reset# = v ss 0.3 v, wp# = v ih 15a i cc7 automatic sleep mode (3, 5) v ih = v cc 0.3 v; v il = v ss 0.3 v, wp# = v ih 15a i acc acc accelerated program current (3) ce# = v il , oe# = v ih acc pin 10 20 ma v cc pin 30 60 ma v il1 input low voltage 1(5, 6) ?0.5 0.8 v v ih1 input high voltage 1 (5, 6) 1.9 v cc + 0.5 v v il2 input low voltage 2 (5, 7) ?0.5 0.3 x v io v v ih2 input high voltage 2 (5, 7) 1.9 v io + 0.5 v v hh voltage for acc program acceleration v cc = 2.7 ?3.6 v 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7 ?3.6 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min = v io 0.15 x v io v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min = v io 0.85 v io v v oh2 i oh = ?100 a, v cc = v cc min = v io v io ?0.4 v v lko low v cc lock-out voltage (8) 2.3 2.5 v
38 am29lv641mh/l december 21, 2005 datasheet test conditions table 12. test specifications note: if v io < v cc , the reference level is 0.5 v io . key to switching waveforms 2.7 k c l 6.2 k 3.3 v device under te s t note: diodes are in3064 or equivalent figure 12. test setup test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels (see note) 1.5 v output timing measurement reference levels 0.5 v io v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 0.5 v io v output measurement level input note: if v io < v cc , the input measurement reference level is 0.5 v io . figure 13. input waveforms and measurement levels
december 21, 2005 am29lv641mh/l 39 datasheet ac characteristics read-only operations notes: 1. not 100% tested. 2. see figure 12 and table 12 for test specifications. 3. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . parameter description test setup speed options jede c std. 90r 101r, 101 112r 112 120r 120 unit t avav t rc read cycle time (note 1) min 90 100 110 120 ns t avqv t acc address to output delay ce#, oe# = v il max 90 100 110 120 ns t elqv t ce chip enable to output delay oe# = v il max 90 100 110 120 ns t pac c page access time max 25 30 30 40 30 40 ns t glqv t oe output enable to output delay max 25 30 30 40 30 40 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh reset# t df figure 14. read operation timings
40 am29lv641mh/l december 21, 2005 datasheet ac characteristics figure 15. page read timings a21 - a2 ce# oe# a1 - a0 data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
december 21, 2005 am29lv641mh/l 41 datasheet ac characteristics hardware reset (reset#) notes: 1. not 100% tested. 2. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . ac characteristics parameter description all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh reset# t df figure 16. read operation timings
42 am29lv641mh/l december 21, 2005 datasheet reset# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp figure 17. reset timings
december 21, 2005 am29lv641mh/l 43 datasheet ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words programmed. 4. effective write buffer specification is based upon a 16-word write buffer operation. 5. word programming specification is based upon a single wo rd programming operation not utilizing the write buffer. 6. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . 7. when using the program suspend/resume featur e, if the suspend command is issued within t poll , t poll must be fully re-applied upon resuming the programming operat ion. if the suspend command is issued after t poll , t poll is not required again prior to reading the status bits upon resuming. parameter speed options jedec std. description 90r 101 112 120 unit t avav t wc write cycle time (note 1) min 90 100 110 120 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 352 s effective word program time, using the write buffer (notes 2, 4) ty p 2 2 s effective accelerated word program time, using the write buffer (notes 2, 4) typ 17.6 s single word program operat ion (note 2, 5) typ 100 s accelerated single word programming operation (note 2, 5) ty p 9 0 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s t poll program valid before status polling (note 7) max 4 s
44 am29lv641mh/l december 21, 2005 datasheet ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa t poll n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. figure 18. program operation timings acc t vhh v hh v il or v ih v il or v ih t vhh figure 19. accelerated program timing diagram
december 21, 2005 am29lv641mh/l 45 datasheet ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data notes: 1. sa = sector address (for sector erase), va = valid addr ess for reading status data (see ?write operation status?. 2. these waveforms are for the word mode. figure 20. chip/sector erase operation timings
46 am29lv641mh/l december 21, 2005 datasheet ac characteristics we# ce# oe# high z t oe high z dq15 and dq7 dq14?dq8, dq6?dq0 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc t poll note: va = valid address. illustration shows fi rst status cycle after command sequence, la st status read cycle, and array data read cycle. figure 21. data# polling timings (during embedded algorithms)
december 21, 2005 am29lv641mh/l 47 datasheet ac characteristics oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status note: va = valid address; not required for dq 6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 22. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an addres s within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 23. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
48 am29lv641mh/l december 21, 2005 datasheet ac characteristics temporary sector unprotect notes: 1. not 100% tested. 2. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# t vidr t rsp program or erase command sequence figure 24. temporary sector group unprotect timing diagram
december 21, 2005 am29lv641mh/l 49 datasheet ac characteristics sector group protect: 150 s, sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect or unprotect verify v id v ih * for sector group protect, a6:a0 = 0xx 0010. for sector group unprotect, a6:a0 = 1xx0010. figure 25. sector group protect and unprotect timing diagram
50 am29lv641mh/l december 21, 2005 datasheet ac characteristics alternate ce# controlled erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words programmed. 4. effective write buffer specification is based upon a 16-word write buffer operation. 5. word programming specification is based upon a single wo rd programming operation not utilizing the write buffer. 6. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . 7. when using the program suspend/resume featur e, if the suspend command is issued within t poll , t poll must be fully re-applied upon resuming the programming operat ion. if the suspend command is issued after t poll , t poll is not required again prior to reading the status bits upon resuming. parameter speed options jedec std. description 90r 101, 101r 112, 112r 120, 120r unit t avav t wc write cycle time (note 1) min 90 100 110 120 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 352 s effective word program time, using the write buffer (notes 2, 4) ty p 2 2 s effective accelerated word program time, using the write buffer (notes 2, 4) typ 17.6 s single word program operation (note 2, 5) typ 100 s accelerated single word programming operation (note 2, 5) ty p 9 0 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t rh reset high time before write (note 1) min 50 ns t poll program valid before status polling (note 7) max 4 s
december 21, 2005 am29lv641mh/l 51 datasheet ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7#, d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy dq15 t poll notes: 1. figure indicates last two bus cycl es of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. figure 26. alternate ce# controlled write (erase/program) operation timings
52 am29lv641mh/l december 21, 2005 datasheet erase and programming performance 1. typical program and erase times as sume the following conditions: 25 c, 3.0 v v cc . programming specifications assume that all bits are programmed to 00h. 2. maximum values are measured at v cc = 3.0 v, worst case temperature. maximum values are valid up to and including 100,000 program/erase cycles. 3. word programming specification is based upon a single word /byte programming operation not utilizing the write buffer. 4. for 1-16 words programmed in a single write buffer programming operation. 5. effective write buffer specification is calculated on a per-word basis for a 16-word write buffer operation. 6. in the pre-programming step of the embedded erase algor ithm, all bits are programmed to 00h before erasure. 7. system-level overhead is the time required to execute the command sequence(s) for the program command. see table 10 for further information on command definitions. 8. the device has a minimum erase and program cycle endurance of 100,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 15 sec excludes 00h programming prior to erasure (note 6) chip erase time 64 128 sec single word program time (note 3) 100 800 s excludes system level overhead (note 7) accelerated single word program time (note 3) 90 720 s total write buffer program time (note 4) 352 1800 s effective word program time, using the write buffer (note 5) 22 113 s total accelerated write buffer program time (note 4) 282 1560 s effective accelerated word program time, using the write buffer (note 4) 17.6 98 s description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma
december 21, 2005 am29lv641mh/l 53 datasheet tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf parameter description t est conditions min unit minimum pattern data retention time 150 c10years 125 c20years
54 am29lv641mh/l december 21, 2005 datasheet physical dimensions ts 048?48-pin standard thin small outline package dwg rev aa; 10/99
december 21, 2005 am29lv641mh/l 55 datasheet physical dimensions tsr048?48-pin reverse thin small outline package dwg rev aa; 10/99
56 am29lv641mh/l december 21, 2005 datasheet revision summary revision a (august 3, 2001) initial release as abbreviated advance information data sheet. revision a+1 (october 3, 2001) global added 120 ns speed option. ordering information changed operating voltage range for 90 ns device. physical dimensions added section. revision b (march 14, 2002) global expanded data sheet to full specification version. revision b+1 (april 26, 2002) mirrorbit 64 mbit device family deleted am29lv641mt/b. figure 2, in-system sector group protect/unprotect algorithms added a3 and a2 address requirement. sector group protection/unprotection deleted reference to alternate method of sector pro- tection. autoselect command substituted text with id code table for easier refer- ence. table 10, command definitions combined notes 4 and 5 from revision b. corrected number of cycles indicated for write-to-buffer and au- toselect device id command sequences. figure 25, sector group protect and unprotect timing diagram in the note, added a3 and a2 address requirement. revision b+2 (august 1, 2002) mirrorbit 64 mbit device family added 64 fortified bga to table. program suspend/program resume command sequence changed program operation wait time from 1ms to 15 s. figure 5. program suspend/program resume changed wait from 1ms to 15 s. erase resume/erase resume commands added a maximum of 20 s. alternate ce# controlled erase and program operations added t rh parameter to table. special package handling instructions modified the special handling wording. dc characteristics table deleted the i acc specification row. cfi changed text in the third paragraph of cfi to read ?reading array data.? revision b+3 (september 10, 2002) product selector guide added note 2. ordering information added note 1. sector erase command sequence deleted statement that describes the outcome of when the embedded erase operation is in progress. revision b+4 (october 15, 2002) erase and programming performance changed values for typical and maximum times on word program time and write buffer program time to tbd. inserted tbd for maximum chip erase time. revision b+5 (november 26, 2002) product selector guide and read-only characteristics added a 30 ns option to t pac c and t oe standard for the 112r and 120r speed options. customer lockable: secsi sector not programmed or protected at the factory. added second bullet, secsi sector-protect verify text and figure 3. secsi sector flash memory region, and enter secsi sector/exit secsi sector command sequence noted that the acc function and unlock bypass modes are not available when the secsi sector is enabled.
december 21, 2005 am29lv641mh/l 57 datasheet byte/word program command sequence, sector erase command sequence, and chip erase command sequence noted that the secsi sector, autoselect, and cfi func- tions are unavailable when a program or erase opera- tion is in progress. common flash memory interface (cfi) changed cfi website address figure 6. program suspend/program resume change wait time to 15 s. cmos compatible added i lr row to table changed v ih1 and v ih2 minimum to 1.9. removed typos in notes. hardware reset, cmos tables, erase and program operations, temporary sector unprotect, and alternate ce# controlled erase and program operations added note. revision b+6 (february 16, 2003) distinctive characteristics corrected performance characteristics. product selector guide added note 3. ordering information corrected valid combination to reflect speed option changes. added note. ac characteristics removed 90, 90r speed option. added note input values in the t whwh 1 and t whwh 2 parameters in the erase and program options table that were previ- ously tbd. also added notes 5 and 6. input values in the t whwh 1 and t whwh 2 parameters in the alternate ce# controlled erase and program op- tions table that were previously tbd. also added notes 5. erase and programming performance input values into table that were previously tbd. added note 3 and 4. revision b+7 (june 12, 2003) ordering information added 90r speed grade, modified note. erase and programming performance modified table, inserted values for typical. revision b+8 (february 13, 2004) table 1 device bus operations modified acc column, replaced instances of x to l/h. word/byte program command sequence removed reference to byte. erase suspend/erase resume commands added note on flash device performance during sus- pend/erase mode . table 10 command definitions modified program/erase suspend and program/erase resume from ba to xxx (don?t care). ac characteristics - erase and program operations added t poll information and note. ac characteristics - alternate ce# controlled erase and program operations added t poll information and note. ac characteristics figures added t poll timing to figure 18, program operation timings ; figure 21, data# polling timings (during embedded algorithms) ; and figure 26, alternate ce# controlled write (erase/program) operation timings . erase and programming performance removed reference to byte. trademarks updated. revision b+9 (august 23, 2004) added max programming specifications. added notation referencing superseding documenta- tion. revision b+10 (december 21, 2005) global this product has been retired and is not available for designs. for new and current designs, s29gl064a supersedes am29lv641m h/l and is the factory-rec- ommended migration path. please refer to the s29gl064a datasheet for specifications and ordering information. availability of this document is retained for reference and historical purposes only.
58 am29lv641mh/l december 21, 2005 datasheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufac tured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a seri ous effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semic onductor de- vices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating s afety design mea- sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abn ormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on expor t under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. trademarks copyright ? 2004-2005 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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